1. Field of the Invention
The present invention relates to a data processor, and more specifically to a method of locating and controlling a memory device provided in the data processor.
2. Description of Related Art
A typical conventional data processor includes a central processing unit (CPU) for executing data processing. The CPU is coupled to an address bus used to supply an address to an external device and a data bus for transferring data between the CPU and the external device. In addition, the CPU is coupled to a control bus used for controlling the external device. One typical CPU is adapted to handle a memory space in such a manner that a plurality of consecutive memory areas are treated as a one block. In this CPU, a width of an internal data bus is larger than a width of an external data bus. Therefore, a plurality of external bus cycles can be generated in response to one internal bus cycle. This type of CPU can be exemplified by Intel's microprocessor i8088 and a CPU including a cache controller therein. As known, the cache controller has adopted a data exchange procedure in which a memory space is divided into a plurality of blocks, and data exchange or transfer between a cache memory and an external memory is collectively executed in units of blocks.
In addition, the data bus is coupled to a plurality of DRAMs (dynamic random access memory), which constitute external memories for the CPU. Each of the DRAMs is controlled by one corresponding DRAM controller coupled to the address bus. Each DRAM controller is controlled by a control logic which is coupled to the CPU through a control bus in order to interface an operating timing between the control bus and the external device such as the DRAMs and the DRAM controller. Typically, the control logic supplies a common memory read signal and a common memory write signal to all the DRAM controllers. The DRAM controllers are also controlled by a decoder coupled to the address bus so that one of the DRAM controllers is selectively activated in response to a chip select signal generated by the decoder on the basis of the result of decoding of an address on the address bus.
The DRAM is configured to be capable of executing a high speed page mode operation, in which if a row address does not, change, a data exchange can be executed by changing only a column address and activating a column address strobe again. In a normal access mode, a row address and a column address are applied to the DRAM by executing an address input by two times. Therefore, since the input of the row address is unnecessary, the data exchange can be correspondingly executed at a high speed.
On the other hand, the DRAM has one restriction in which once a row address strobe is activated, a precharge period in which the row address strobe is made inactive is required. If the precharge period is not satisfied, a content of the DRAM will be lost.
Now, assuming that the address bus is composed of 32 bits, and two 1M DRAMs are used, an address of 0000 0000.sub.h to 000F FFFF.sub.h is assigned to a first DRAM, and an address of 0010 0000.sub.h to 001F FFFF.sub.h is assigned to a second DRAM, in a memory map of the data processor. Here, the suffix "h" means a hexadecimal notation. In addition, the CPU can access to the external device with units of block each of which includes a plurality of units of processing, similarly to the type including the cache memory therein. Here, the unit of processing is called a "word". For example, one block includes four words.
Under the above mentioned conditions, an operation of the conventional data processor will be discussed. At a T1 clock of a first bus cycle, an address is supplied to the address bus, and decoded by the decoder. If the supplied address designates the first DRAM, the decoder outputs an active chip select signal to a first DRAM controller associated with the first DRAM. On the other hand, a memory access is outputted to the control bus and converted by the control logic into an active memory read signal or into an active memory write signal. Now, assume that the memory read signal has been activated.
In response to the active chip select signal and the active memory read signal, the first DRAM controller associated with the first DRAM is activated. As a result, at a falling of the T1 clock, the row address strobe supplied to the first DRAM is activated by the first DRAM controller and thereafter maintained in an active condition. Then, the first DRAM controller supplies an address signal to the first DRAM during a high level period of the T1 clock. At a rising of a T2 clock following the T1 clock, the column address strobe supplied to the first DRAM is activated, so that a content of the first DRAM is outputted to the data bus. At an end of a low level period of the T2 clock, the data exchange is completed, and a first TB clock following the T2 clock rises. The TB clock is used in the high speed page mode operation, and makes it possible to execute the data exchange with only one clock. At a rising of the first TB clock, the column address strobe supplied to the first DRAM is inactivated, and a next address is supplied to the first DRAM during a high level period of the TB clock. At a falling of the first TB clock, the column address strobe supplied to the first DRAM is activated, and the a second data exchange is executed during a low level period of the TB clock. Succeeding to the first TB clock, second and third clocks are generated so that the same memory reading operation (the data exchange) is executed three times. As a result, the data exchange is executed four times in total by the T1 and T2 clocks and the succeeding first to third TB clocks.
Following the first bus cycle, a second bus cycle starts, and a T1 clock of the second bus cycle rises at an end of the low level period of the third TB clock of the first bus cycle. At the T1 clock, a next address is supplied to the address bus so that a memory access will be started. However, at a falling of the T1 clock of the second bus cycle, the row column strobe supplied to the first DRAM is inactivated, and maintained in an inactive condition for a period corresponding to one clock period, since a period for the precharging is required to have one clock period. As a result, the row column strobe supplied to the first DRAM is activated at a falling of the T2 clock of the second bus cycle. Namely, the starting of the memory access in the second bus cycle is delayed from the starting of the memory access in the first bus cycle by a period of time corresponding to one clock. Because of this, a TW clock is inserted between the T2 clock and the first TB clock in the second bus cycle, so that the CPU is brought into a wait condition so as to adjust the timing. This adjustment is controlled by the control logic.
As seen from the above, when the same bank of the memory is continuously accessed by the CPU, the data exchange, which will be completed with five clocks in ordinary cases, requires six clocks. As a result, the processing capacity of the data processor will correspondingly decrease. If first and second accesses are made to different banks, respectively, a second access can be completed with five clocks. However, considering a processing situation of the CPU, an instruction reading operation is of course executed for consecutive memory banks, and data processed by the CPU is collectively stored in some region of the memory (localization of access region). Therefore, the possibility of access to the same bank is higher than the possibility of access to different banks. As a result, opportunity of the six clock access is much.
The above mentioned operation time was made on the basis of clocks. In fact, however, various operating timings of different DRAMs coupled to the CPU must be satisfied. For example, an access period of time from the activation of the column address strobe until the completion of the data exchange must be ensured. Therefore, if the processing capacity of the data processor is increased by increasing the frequency of the clock, the operation based on the T1 and T2 clocks can be adjusted by inserting the TW clock for waiting, but it is not possible to adjust the operation of the TB clock by inserting the TW clock. As a result, there occurs a situation in which the operating timing (for example, the access period of time starting from the activation of the column address strobe) cannot be satisfied. In this situation, the data processor cannot properly operate.
In addition, the DRAM has rapid access mode such as the high speed page mode which is higher than the ordinary access operation. However, ROMs (read only memory) and SRAMs (static random access memory) always require the same access time. In the case that these memories are coupled to the CPU, if the CPU is adapted to execute a first memory access by the T1 and T2 clocks and each of succeeding memory accesses by one TB clock as in the conventional example explained hereinbefore, it is requires that the memory access can be completed by only one clock. As a result, expensive ROMs or SRAMs are required.
Furthermore, if ROMs or SRAMs are used, these memory resources are often located at the outside of the cache coverage. In addition, it is necessary to generate various control signals so that the data exchange between the DRAM and the CPU is executed in the high speed access mode (T1, T2, TB, TB and TB clocks) and the data exchange between the ROM or SRAM and the CPU is executed in a normal access mode (four sets of T1 and T2 clocks). However, if the ROMs or SRAMs are located at the outside of the cache coverage, the performance of the data processor inevitably degrades. If the CPU operates in different modes, the control circuit becomes complicated.